Communication Architecture Synthesis for Multi-bus SoC

Abstract

In the systems on chip (SoC) design, the synthesis of communication architecture constitutes the bottleneck which can affect the performances of the system. Various schemes and protocols can be necessary, just as various topologies of interconnection. To reduce the complexity of the communications refinement, we present in this study a model and a synthesis approach for multi-bus communication architecture containing centralized bridge. The automation of the arbiter synthesis step profited from a detailed attention. This stage generates a hierarchical arbiter integrating various priority arbitration modules. The proposed approach was integrated in a toolbox based environment.